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DRV10983-Q1 Automotive, 12V, 24V Three-Phase, Sensorless BLDC Motor Driver Evaluation Module

The DRV10983Q1EVM evaluation module (EVM) serves as a user-friendly evaluation kit to demonstrate TI's brushless motor driver, DRV10983-Q1. The EVM is a high-performance, power-efficient, cost-effective platform that speeds development for quicker time to market. DRV10983Q1EVM supports sensorless Brushless DC motors for a wide range of automative applications.

具有三态输出的八路缓冲器和线路驱动器

These octal buffers and line drivers feature the performance of the SNx4HC541 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.

低功耗单路反向器闸

The SN74AUP1G04 device is a single inverter gate performs the Boolean function Y = A.

具有三态输出的 16 位总线收发器

This 16-bit (dual-octal) noninverting bus transceiver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

具有三态输出的 16 位总线收发器

This 16-bit (dual-octal) noninverting bus transceiver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

具有三态输出的八路缓冲器/驱动器

These octal bus buffers are designed for 1.65-V to 3.6-V VCC operation. The SN74LVC244A devices are designed for asynchronous communication between data buses.

具有三态输出的八路总线收发器

These octal bus transceivers are designed for 1.65-V to 3.6-V VCC operation. The ’LVC245A devices are designed for asynchronous communication between data buses.

具有三态输出的 16 位缓冲器和线路驱动器

The 'AC16244 are 16-bit buffers/line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

八路总线收发器

This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

八路缓冲器/驱动器

The 74AC11244 is an octal buffer or line driver designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as two 4-bit buffers or one 8-bit buffer, with active-low output-enable (OE\) inputs.

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