LMK00105 是一款高性能、低噪声 LVCMOS 扇出缓冲器，可通过差分、单端或晶振输入实现五路超低抖动时钟。 LMK00105 支持同步输出使能功能，可确保无毛刺脉冲运行。 这款缓冲器具有超低偏斜、低抖动和高电源抑制比 (PSRR) 等诸多优势，因此非常适合各类网络互连、电信、服务器和存储局域网络互连、RRU LO 基准分布、医疗和测试设备应用。
LMK00334 是一款 4 路输出 HCSL 扇出缓冲器，用于高频、低抖动时钟/数据分配和电平转换。 可从两个通用输入或一个晶振输入中选择输入时钟。 所选择的输入时钟被分配到两组 HCSL 输出（每组 2 个）和 1 个 LVCMOS 输出。 LVCMOS 输出具有同步使能输入，在使能或禁用后可实现无短脉冲运行。 LMK00334 由一个 3.3V 内核电源和 3 个独立的 3.3V/2.5V 输出电源供电运行。
The TLC2932A is designed for phase-locked loop (PLL) systems and is composed of a voltage-controlled oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage. The high speed PFD with internal charge pump detects the phase difference between the reference frequency input and signal frequency input from the external counter. Both the VCO
The CDCVF855 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to 4 differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.
The CDC204 contains six independent inverters. The device performs the Boolean function Y = A\. It is designed specifically for applications requiring low skew between switching outputs.
The CDC203 contains six independent inverters. The device performs the Boolean function Y = A\. It is designed specifically for applications requiring low skew between switching outputs.
The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50-transmission lines.
CDC1104 是一款 1 个至 4 个可配置时钟缓冲器。 此器件接受一个输入参考时钟并创建 4 个缓冲输出时钟，这些时钟的输出频率等于输入时钟频率的1.5倍。 四个控制输入，时钟输出的S1，S2，S3，S4可配置相位。