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超低抖动时钟发生器系列

LMK03318 是一款超低噪声 PLLatinumTM 时钟发生器,包含一个集成压控振荡器 (VCO) 的分数 N 频率合成器、灵活的时钟分配/扇出以及可通过引脚选择的配置状态(存储在片上 EEPROM 中)。该器件可为各种千兆位级串行接口和数字器件提供多个时钟,从而通过替代多个振荡器和时钟分配器件来降低物料清单 (BOM) 成本、减小电路板面积、以及提高可靠性。超低抖动可降低高速串行链路中的比特误码率 (BER)。

具有集成 VCO 的精密 0 延迟时钟调节器

The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

1.5-V Phase-Lock Loop Clock Driver

The CDCVF855 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to 4 differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs

具有扩频兼容性的汽车类 PLL 时钟驱动器,用于同步 DRAM 通 用 应用领域。

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications

The CDCUA877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the

1.8-V Phase Lock Loop Clock Driver

The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the

高性能、低相位噪声、低偏移的时钟同步器(使参考时钟与 VCXO 同步)

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O

CDCEL824 可编程 2 PLL 时钟合成器

CDCEL824 是一款基于锁相环 (PLL) 的模块化、低成本、高性能可编程时钟合成器/乘法器/除法器。 该器件最多可从单输入频率中生成四个输出时钟。 在系统内最多可使用两个独立可配置 PLL 在任何时钟频率下(最高可达 201MHz)对各输出进行编程。

10 路输出低抖动时钟同步器和抖动消除器

"The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The following relationship applies to the dividers: Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)"

高性能、低相位噪声、低偏移的时钟同步器(使参考时钟与 VCXO 同步)

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can